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r4300 [2019/02/12 18:11] shygoo better information on rcp interrupt masking |
r4300 [2019/05/06 17:54] (current) shygoo [Interrupts] clarify MI_INTR_MASK_REG usage |
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| ==== Interrupts ==== | ==== Interrupts ==== | ||
| ^Cause bit^Source ^ | ^Cause bit^Source ^ | ||
| - | |IP7 |Timer interrupt| | ||
| - | |IP6 |Int4 pin <color lightgreen>(N64: RDB Write)</color>| | ||
| - | |IP5 |Int3 pin <color lightgreen>(N64: RDB Read)</color>| | ||
| - | |IP4 |Int2 pin <color lightgreen>(N64: Pre-NMI (Reset button))</color>| | ||
| - | |IP3 |Int1 pin <color lightgreen>(N64: Cartridge)</color>| | ||
| - | |IP2 |Int0 pin <color lightgreen>(N64: RCP)</color>| | ||
| - | |IP1 |Set by software| | ||
| |IP0 |Set by software| | |IP0 |Set by software| | ||
| + | |IP1 |Set by software| | ||
| + | |IP2 |Int0 pin <color lightgreen>(N64: RCP)</color>| | ||
| + | |IP3 |Int1 pin <color lightgreen>(N64: Cartridge)</color>| | ||
| + | |IP4 |Int2 pin <color lightgreen>(N64: Pre-NMI (Reset button))</color>| | ||
| + | |IP5 |Int3 pin <color lightgreen>(N64: RDB Read)</color>| | ||
| + | |IP6 |Int4 pin <color lightgreen>(N64: RDB Write)</color>| | ||
| + | |IP7 |Timer interrupt| | ||
| - | * The Timer interrupt (IP7) is generated when the Count and Compare registers are equal. | ||
| * Software interrupts (IP1:IP0) are generated when software manually sets the Cause register's IP1 or IP0 bit to 1 using an MTC0 instruction. | * Software interrupts (IP1:IP0) are generated when software manually sets the Cause register's IP1 or IP0 bit to 1 using an MTC0 instruction. | ||
| - | * Interrupts may be masked by setting the corresponding IM bits of the Status register to 0. | + | * The Timer interrupt (IP7) is generated when the Count and Compare registers are equal. |
| + | * Interrupts may be masked by setting the respective IM bits of the Status register to 0. | ||
| <color lightgreen> | <color lightgreen> | ||
| - | On the Nintendo 64, IP2 represents an RCP (Reality Coprocessor) interrupt. When an RCP interrupt occurs, a flag representing the specific RCP interface is written to MI_INTR_REG (0x04300008). | + | On the Nintendo 64, IP2 represents an RCP (Reality Coprocessor) interrupt. When an RCP interrupt occurs, a flag representing the specific RCP interface may be read from MI_INTR_REG (0x04300008). |
| </color> | </color> | ||
| ^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ||
| Line 403: | Line 403: | ||
| <color lightgreen> | <color lightgreen> | ||
| - | RCP-specific interrupts may be masked or unmasked by writing one or more of the following values to MI_INTR_MASK_REG (0x0430000C). | + | RCP-specific interrupts may be enabled or disabled by writing one or more of the following values to MI_INTR_MASK_REG (0x0430000C). |
| </color> | </color> | ||
| ^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ^<color lightgreen>Bit</color>^<color lightgreen>Name</color>^<color lightgreen>Description</color>^ | ||
| - | |<color lightgreen>0x0001</color>|<color lightgreen>MI_INTR_MASK_CLR_SP</color>|<color lightgreen>Clear SP mask</color>| | + | |<color lightgreen>0x0001</color>|<color lightgreen>MI_INTR_MASK_CLR_SP</color>|<color lightgreen>Disable SP interrupts</color>| |
| - | |<color lightgreen>0x0002</color>|<color lightgreen>MI_INTR_MASK_SET_SP</color>|<color lightgreen>Set SP mask</color>| | + | |<color lightgreen>0x0002</color>|<color lightgreen>MI_INTR_MASK_SET_SP</color>|<color lightgreen>Enable SP interrupts</color>| |
| - | |<color lightgreen>0x0004</color>|<color lightgreen>MI_INTR_MASK_CLR_SI</color>|<color lightgreen>Clear SI mask</color>| | + | |<color lightgreen>0x0004</color>|<color lightgreen>MI_INTR_MASK_CLR_SI</color>|<color lightgreen>Disable SI interrupts</color>| |
| - | |<color lightgreen>0x0008</color>|<color lightgreen>MI_INTR_MASK_SET_SI</color>|<color lightgreen>Set SI mask</color>| | + | |<color lightgreen>0x0008</color>|<color lightgreen>MI_INTR_MASK_SET_SI</color>|<color lightgreen>Enable SI interrupts</color>| |
| - | |<color lightgreen>0x0010</color>|<color lightgreen>MI_INTR_MASK_CLR_AI</color>|<color lightgreen>Clear AI mask</color>| | + | |<color lightgreen>0x0010</color>|<color lightgreen>MI_INTR_MASK_CLR_AI</color>|<color lightgreen>Disable AI interrupts</color>| |
| - | |<color lightgreen>0x0020</color>|<color lightgreen>MI_INTR_MASK_SET_AI</color>|<color lightgreen>Set AI mask</color>| | + | |<color lightgreen>0x0020</color>|<color lightgreen>MI_INTR_MASK_SET_AI</color>|<color lightgreen>Enable AI interrupts</color>| |
| - | |<color lightgreen>0x0040</color>|<color lightgreen>MI_INTR_MASK_CLR_VI</color>|<color lightgreen>Clear VI mask</color>| | + | |<color lightgreen>0x0040</color>|<color lightgreen>MI_INTR_MASK_CLR_VI</color>|<color lightgreen>Disable VI interrupts</color>| |
| - | |<color lightgreen>0x0080</color>|<color lightgreen>MI_INTR_MASK_SET_VI</color>|<color lightgreen>Set VI mask</color>| | + | |<color lightgreen>0x0080</color>|<color lightgreen>MI_INTR_MASK_SET_VI</color>|<color lightgreen>Enable VI interrupts</color>| |
| - | |<color lightgreen>0x0100</color>|<color lightgreen>MI_INTR_MASK_CLR_PI</color>|<color lightgreen>Clear PI mask</color>| | + | |<color lightgreen>0x0100</color>|<color lightgreen>MI_INTR_MASK_CLR_PI</color>|<color lightgreen>Disable PI interrupts</color>| |
| - | |<color lightgreen>0x0200</color>|<color lightgreen>MI_INTR_MASK_SET_PI</color>|<color lightgreen>Set PI mask</color>| | + | |<color lightgreen>0x0200</color>|<color lightgreen>MI_INTR_MASK_SET_PI</color>|<color lightgreen>Enable PI interrupts</color>| |
| - | |<color lightgreen>0x0400</color>|<color lightgreen>MI_INTR_MASK_CLR_DP</color>|<color lightgreen>Clear DP mask</color>| | + | |<color lightgreen>0x0400</color>|<color lightgreen>MI_INTR_MASK_CLR_DP</color>|<color lightgreen>Disable DP interrupts</color>| |
| - | |<color lightgreen>0x0800</color>|<color lightgreen>MI_INTR_MASK_SET_DP</color>|<color lightgreen>Set DP mask</color>| | + | |<color lightgreen>0x0800</color>|<color lightgreen>MI_INTR_MASK_SET_DP</color>|<color lightgreen>Enable DP interrupts</color>| |
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r4300.1549995060.txt.gz · Last modified: 2019/02/12 18:11 by shygoo